The present invention relates to "passive" integrated circuits included in a portable support. Here, a "passive" integrated circuit designates a circuit with no internal microprocessor but comprising only a memory and decoding means for, in response to a limited number of control signals, sequentially accessing successive cases of the memory and achieving in the memory read, write or erase operations.
Hereinafter, for the sake of simplicity, memory cards only will be referred to because they are the most broadly used support, but it is clear that any other portable support can be used. Thus, below, "memory card" designates the assembly of an integrated circuit, its connecting terminals and any portable support that can be associated to a reader.
A common application of memory cards is prepaid telephone cards. In such cards, memory cases are initially set to a predetermined state, and this state is modified in response to external pulses corresponding, for example, to telephone units or to pay units for any service provided by a reader into which the card is inserted.
The invention more particularly relates to cards in which the data counting memory is an electrically erasable memory, for example an EEPROM-type memory, that is, an Electrically Erasable Programmable Read Only Memory.
FIG. 1 very schematically shows the main components of a semiconductor memory usable in a memory card of this type. Conventionally, this card is associated to a reader with which the card communicates through six connecting pads: two power supply pads V.sub.SS and V.sub.CC, an output pad OUT and three programmation pads A, ST and B. Programmation pads provide signals to an array of logic circuits or programmable logic array 1 to control a column decoder 2 (Y DEC) and a line decoder 3 (X DEC) both associated to an EEPROM 4. Logic circuits 1 also enable, as a function of control signals, to set the memory in read state (R), write state (W) or erase state (E). In read state, the addressed memory case is read, that is, its state is provided to the OUT pad. In write state, the state of the addressed memory case is set to 1. In erase state, a set of simultaneously addressed cases is reset. More particularly, control pads A, ST and B are generally provided to receive either one of three control orders: a reset order which establishes a positioning on the address of the first memory bit, a read order which enables incrementing the memory address and outputting the value of the addressed case, and a programmation order which enables reversing the state of the addressed case or cases to achieve a write or erase operation. According to a characteristic of this type of memory, it is not possible to simultaneously address in read, write or erase mode distinct locations of the memory.
One of the advantages of an EEPROM is that the memory can be arranged in an abacus-type system. This means that the memory is arranged in several levels each comprising a determined number of cases. Each time a lower rank level is full, a case of immediately upper rank level is enabled and the cases of the lower rank level are erased. Thus, for example, with three 8-case levels, at least 8.times.8.times.8 data can be counted instead of 8+8+8 data only if the memory is not erasable. The state of the art and the invention will be described hereafter in the case of three levels each comprising eight cases, but it will be clear to those skilled in the art that a larger number of levels can be used and that the levels will not necessarily have the same number of cases. Generally, it is possible to provide p levels each comprising n.sub.i (i=1 . . . p) cases; thus, it will be possible to store in the memory n.sub.1 .times.n.sub.2 .times.. . . .times.n.sub.p data. By way of example, one will only consider a logic configuration wherein lower rank levels are sequentially erased after writing is achieved in an upper rank register.
The basic arrangement of an abacus-type memory is illustrated in FIG. 2 which shows three 8-case levels 10, 11 and 12 addressable through a column decoder (Y DEC) and a rank decoder (X DEC).
FIGS. 3A, 3B and 3C show a first exemplary filling of levels or registers arranged as an abacus-counter. In FIG. 3A, the lower rank level 10 is full, and levels 11 and 12 are empty. At the step illustrated in FIG. 3B, once level 10 is filled, decoders X and Y set the addressing to the lower case of level 11 and a "1" is written in this level. At the step of FIG. 3C, the whole content of level 10 is erased. Then writing is resumed at the lower rank case of level 10 (not shown).
Of course, these successive addressing operations are ensured by the reader associated to the card which comprises logic circuits adapted to achieve these operations. In particular, the reader first starts, when a card is inserted therein, reading the content of all memories to determine the card state and setting the addressing to achieve. Thus, the reader "knows" in which filling state the various levels are, and can ensure the proper addressing control. However, as indicated above, it is only possible to achieve at a determined period a read, write or erase operation, that is why the transition from the state shown in FIG. 3A to the state shown in FIG. 3C has to be achieved by passing through the intermediate state shown in FIG. 3B.
FIGS. 4A-4E illustrate other exemplary successive states of the memory levels. In FIG. 4A, levels 10 and 11 are full and three cases of level 12 have been filled. At the step shown in FIG. 4B, an additional bit is written in level 12. At the step shown in FIG. 4C, the content of level 11 is erased. At the step illustrated in FIG. 4D, an additional bit is written in level 11. During the step shown in FIG. 4E, the content of level 10 is erased. The writing of a 1 at the step of FIG. 4D enables a storing operation by multiples of 8 instead of 9; moreover, the logic circuits of the reader "know" that, as soon as a datum is written in register 12, at least one 1 must exist in register 11. This can be used to detect a possible error.
The above description corresponds to the state of the art in order to exemplify the field of application of the invention.
The above described arrangement has a drawback; namely, if for any reason, card processing is abruptly interrupted during the state illustrated in FIGS. 3B, 4B or 4D, that is, when the levels with a lower rank than the one in which a datum has just been written have not yet been erased, the card will remain in this state when it is inserted again into the reader. Hence, the memory will have been charged with a number of units higher than the service that has been effectively provided (8 excessive units in the case of FIGS. 3B or 4D, 8.times.8=64 units in the case illustrated in FIG. 4B). This drawback is particularly liable to occur in modern card readers in which the card is not swallowed by the reader but remains apparent, that is, the user can abruptly take out his card at an intermediate state corresponding to FIGS. 3B or 4B-4D. The user will then be unduly charged.